Salicided gate for virtual ground arrays
US6730564B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2002 |
| Grant date | May 4, 2004 |
| Priority date | — |
| Expiry date | Aug 12, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/954
Abstract
The present invention provides a process for saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the invention, saliciding takes place prior to patterning one or more layers of a memory cell stack. The unpatterned layers protect the substrate between word lines from becoming salicided. The invention provides virtual ground array flash memory devices with doped and salicided word lines, but no shorting between bit lines, even in virtual ground arrays where there are no oxide island isolation regions between word lines. Potential advantages of such structures include reduced size, reduced number of processing steps, and reduced exposure to high temperature cycling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.