Method of patterning capacitors and capacitors made thereby
US6734057B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2002 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Sep 27, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31122
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a ferroelectric capacitor, in particular for use in a FeRAM or high-k DRAM application, and a capacitor made by the method. The method comprises forming a first layer which is patterned, for example by a reactive ion etching method. A ferroelectric material is then formed over the patterned first layer. The morphology of the ferroelectric material will be dependent upon the patterning of the first layer. The ferroeletric layer is then patterned, for example using a wet etching or a reactive ion etching method. The etching will depend upon the morphology of the ferroelectric layer. After etching the ferroelectric layer, a conductive layer is provided over the ferroelectric layer to form a first electrode of the capacitor. If the first layer is a conductive layer, this forms the second electrode. If the first layer is a non-conductive layer, the conductive layer is patterned to form both the first and second electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.