Non-volatile memory cell and fabrication method

US6734063B2 · kind B2 · utility

Assignees

• Infineon Technologies AG · DE
• Ingentix GmbH & Co. KG · DE

Inventors

• Josef Willer · Riemerling, DE
• Franz Hofmann · Munich, DE
• Armin Kohlhase · Neubiberg, DE
• Christoph Ludwig · Radeberg, DE

Key dates

• Filing date: Jul 22, 2002
• Grant date: May 11, 2004
• Expiry date: Jul 22, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

Memory cell transistors with back-channel isolation are produced without using an SOI substrate. With the word line stack acting as a mask, the semiconductor material is etched on both sides of the world line, first anisotropically and then isotropically to widen the etch hole and form an undercut beneath the gate electrode and at a distance from the ONO storage layer forming the gate dielectric. The undercut is filled, whereby a buried oxide layer of at least 20 nm maximum thickness is formed underneath the channel region. The latter is p-doped at a density of at least 1017 cm−3.