Trench buried bit line memory devices
US6734482B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2002 |
| Grant date | May 11, 2004 |
| Priority date | — |
| Expiry date | Nov 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
Abstract
A memory device such as a 6F2 memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.