Chip scale package and manufacturing method
US6737300B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2002 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Jun 1, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49171
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip scale package mainly comprises a substrate attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive film (ACF). The substrate is provided with a plurality of contact pads on the lower surface thereof and a plurality of solder pads on the upper surface thereof wherein the contact pads are electrically coupled to corresponding solder pads. A plurality of metal bumps provided on the contact pads of the substrate. The metal bumps on the substrate are electrically coupled to corresponding bonding pads on the chip through the ACF. The side portions of the substrate and the ACF are sealed in a package body. The present invention further provides a method of making the chip scale package at the wafer level. The method is characterized by attaching substrates onto the chips of a wafer one by one so as to greatly reduce the problems associated with CTE mismatch between the wafer and the substrate thereby significantly enhancing the product yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.