Power reduction for delay locked loop circuits
US6737897B2 · kind B2 · utility
19Cited by
4References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2002 |
| Grant date | May 18, 2004 |
| Priority date | — |
| Expiry date | Aug 29, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop circuit includes a plurality of delay cells connected in series. Each of the delay cells connects to an input node which provides a clock signal. A shift register selects one of the delay cells to allow the clock signal to enter the selected delay cell and propagate to an output node, such that internal gates of delay cells preceding the selected delay cell are not toggling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.