Planarization process for semiconductor substrates
US6743724B2 · kind B2 · utility
4Cited by
61References
45Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2001 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Nov 10, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31053
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing semiconductor devices using an improved chemical mechanical planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved chemical mechanical planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer filling in between the surface irregularities prior to the planarization of the surface through a chemical mechanical planarization process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.