Method and apparatus for facilitating process-compliant layout optimization
US6745372B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2002 |
| Grant date | Jun 1, 2004 |
| Priority date | — |
| Expiry date | Apr 5, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the invention provides a system that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size. During operation, the system receives a representation of a target layout for the integrated circuit, wherein the representation defines a plurality of shapes that comprise the target layout. Next, the system simulates effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout. The system then identifies problem areas in the simulated printed image that do not meet a specification. Next, the system moves corresponding shapes in the target layout to produce a new target layout for the integrated circuit, so that a simulated printed image of the new target layout meets the specification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.