Integrated circuit and laminated leadframe package
US6747341B2 · kind B2 · utility
7Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2002 |
| Grant date | Jun 8, 2004 |
| Priority date | — |
| Expiry date | Sep 18, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (100) includes a semiconductor die (102, 103) and a semiconductor package (101) that has a leadframe (20, 40, 60, 80) for mounting the semiconductor die. The leadframe includes a first laminate (20) whose bottom surface (7) is patterned with leads (106, 107, 131, 132) of the integrated circuit. A second laminate (40) has a bottom surface (3) attached to a top surface (5) of the first laminate to electrically coupling the leads to the semiconductor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.