Precision high-K intergate dielectric layer
US6750066B1 · kind B1 · utility
83Cited by
23References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 8, 2002 |
| Grant date | Jun 15, 2004 |
| Priority date | — |
| Expiry date | Jun 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device which includes a precision high-K dielectric and formed on a semiconductor substrate and a method of forming the same. The semiconductor device includes at least one dielectric layer having a dielectric constant greater than SiO2. The at least one dielectric layer is deposited by atomic layer deposition (ALD). The ALD deposited layer has precise uniformity, thickness and abrupt atomic interfaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.