Integrated test circuit

US6750670B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Thorsten Bucksch · Munich, DE
• Ralf Schneider · Birkenfeld, DE

Key dates

• Filing date: Dec 12, 2002
• Grant date: Jun 15, 2004
• Expiry date: Dec 12, 2022

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/3016
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An integrated test circuit, as part of an integrated circuit, includes phase-shifted test signals fed through inputs A and B. These test signals are conducted through a plurality of cascaded delay elements, the advancing of the first test signal through the delay elements being held and evaluated by the second test signal.