Semiconductor integrated circuit and method for manufacturing the same

US6753231B2 · kind B2 · utility

Assignee

• Renesas Technology Corporation · JP

Inventors

• Shuji Ikeda · Koganei, JP
• Yasuko Yoshida · Sayama, JP
• Masayuki Kojima · Wakayama, JP
• Kenji Shiozawa · Ibaraki, JP
• Mitsuyuki Kimura · Kyoto, JP
• Norio Nakagawa · Koganei, JP
• Koichiro Ishibashi · Warabi, JP
• Yasuhisa Shimazaki · Kodaira, JP
• Kenichi Osada · Tokyo, JP
• Kunio Uchiyama · Kodaira, JP

Key dates

• Filing date: Mar 6, 2003
• Grant date: Jun 22, 2004
• Expiry date: Mar 6, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B10/12

Abstract

An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.