Testing of integrated circuit devices
US6754866B1 · kind B1 · utility
16Cited by
56References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Jun 22, 2004 |
| Priority date | — |
| Expiry date | Nov 10, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device includes a data buffer, coupled to an external connector, providing a data signal on the external connector. A test buffer, coupled to the data buffer, receives the data signal and provides a testing output signal to a delay circuit. The delay circuit receives the testing output signal at a first clock rate internal to the integrated circuit device and compares test data in the testing output signal to expected test signal values. The delay circuit provides a result to an external connector at a second clock rate that is slower than the first clock rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.