Gated semiconductor assemblies

US6756634B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Mark A. Helm · Boise, US
• Mark Fischer · Boise, US
• John T. Moore · Boise, US
• Scott DeBoer · Boise, US

Key dates

• Filing date: Nov 10, 1999
• Grant date: Jun 29, 2004
• Expiry date: Nov 10, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

In one aspect, the invention includes a method of forming a gated semiconductor assembly, comprising: a) forming a silicon nitride layer over and against a floating gate; and b) forming a control gate over the silicon nitride layer. In another aspect, the invention includes a method of forming a gated semiconductor assembly, comprising: a) forming a floating gate layer over a substrate; b) forming a silicon nitride layer over the floating gate layer, the silicon nitride layer comprising a first portion and a second portion elevationally displaced from the first portion, the first portion having a greater stoichiometric amount of silicon than the second portion; and c) forming a control gate over the silicon nitride layer. In yet another aspect, the invention includes a gated semiconductor assembly comprising: a) a substrate; b) a floating gate over the substrate; c) a control gate over the floating gate; and d) an electron barrier layer between the floating gate and the control gate, the electron barrier layer comprising a silicon nitride layer, the silicon nitride layer comprising a first portion and a second portion elevationally displaced from the first portion, the first portio…