System and method for reducing a ground bounce during write by selectively delaying address and data lines with different multiple predetermined amount of delay
US6760855B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2000 |
| Grant date | Jul 6, 2004 |
| Priority date | — |
| Expiry date | Jan 2, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00234
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method and related structure for reducing ground bounce during write operations from a microprocessor. More specifically, the address and data signal lines of the microprocessor are divided into three transmission groups. The first transmission group transitions its data onto the bus lines with no delay. The second transmission group transitions its signal lines onto the bus with a half clock period delay of the core frequency clock. Finally, the third transmission group transitions its signal lines onto the bus with a full clock period delay of the core frequency clock. In this way, parallel writes by the microprocessor have their current sinking associated with that write distributed over an entire clock period of the core frequency clock such that ground bounce associated with that current sinking is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.