Test configuration and test method for testing a plurality of integrated circuits in parallel

US6762611B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Michael Hübner · Weinheim, DE
• Gunnar Krause · Munich, DE
• Justus Kuhn · Birkenfeld, DE
• Jochen Müller · Hersbruck, DE
• Peter Pöchmüller · Birkenfeld, DE
• Jürgen Weidenhöfer · Birkenfeld, DE

Key dates

• Filing date: Dec 5, 2001
• Grant date: Jul 13, 2004
• Expiry date: Dec 5, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318505
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.