Method of manufacture of MOSFET device with in-situ doped, raised source and drain structures

US6774000B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Wesley C. Natzle · New Paltz, US
• Marc W. Cantell · Enosburg Falls, US
• Louis D. Lanzerotti · Burlington, US
• Effendi Leobandung · Stormville, US
• Brian L. Tessier · Poughkeepsie, US
• Ryan Wuthrich · Burlington, US

Key dates

• Filing date: Nov 20, 2002
• Grant date: Aug 10, 2004
• Expiry date: Nov 20, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0275
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A process for manufacturing an FET device. A semiconductor substrate is covered with a gate dielectric layer and with a conductive gate electrode formed over the gate dielectric. Blanket layers of silicon oxide may be added. An optional collar of silicon nitride may be formed over the silicon oxide layer around the gate electrode. Two precleaning steps are performed. Chemical oxide removal gases are then deposited, covering the device with an adsorbed reactant film. The gate dielectric (aside from the gate electrode) is removed, as the adsorbed reactant film reacts with the gate dielectric layer to form a rounded corner of silicon oxide at the base of the gate electrode. One or two in-situ doped silicon layers are deposited over the source/drain regions to form single or laminated epitaxial raised source/drain regions over the substrate protruding beyond the surface of the gate dielectric.