High density semiconductor memory cell and memory array using a single transistor
US6777757B2 · kind B2 · utility
73Cited by
63References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2002 |
| Grant date | Aug 17, 2004 |
| Priority date | — |
| Expiry date | Apr 26, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+ region in the substrate underlying the gate of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.