Integrated circuit memory device and method
US6778441B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2001 |
| Grant date | Aug 17, 2004 |
| Priority date | — |
| Expiry date | Aug 30, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/681
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, Gd2O3, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.