Method of programming a memory cell
US6781885B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2003 |
| Grant date | Aug 24, 2004 |
| Priority date | — |
| Expiry date | Aug 19, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In programming the threshold voltage of a memory cell transistor having a substrate, a gate insulator on the substrate, a floating gate on the gate insulator, an insulating layer on the floating gate, and a control gate on the insulating layer, and a source and drain in the substrate, a voltage difference is applied between the drain and source of the transistor and negative voltage is applied to the substrate of the transistor. An increasing voltage is applied to the control gate of the transistor, and, during application of that increasing voltage, a succession of verification tests are undertaken at a corresponding succession of times separated by chosen time intervals to verify if the transistor has been programmed to a chosen threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.