Lithography correction method and device
US6783904B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2002 |
| Grant date | Aug 31, 2004 |
| Priority date | — |
| Expiry date | Nov 5, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/705
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method (10) for correcting lithography error includes generating (18) data that defines relationships between at least one predetermined design layout parameter and a known minimum required lithographic process capability (e.g. minimum feature spacing), and then using the data to upsize (30) predetermined isolated features or portions of predetermined isolated or semi-isolated features. In some embodiments, the resulting wafer circuit pattern (70) has isolated features (71, 72, 74) that are all larger than a predetermined minimum width. The upsized features are larger in the wafer circuit pattern (70) than they are drawn in a designed database. The method for correcting the lithography error, in some embodiments, is stored on a computer readable storage medium.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.