Method of forming double-gated silicon-on-insulator (SOI) transistors with reduced gate to source-drain overlap capacitance

US6787404B1 · kind B1 · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Yong Meng Lee · Singapore, SG
• Da Jin · Tianqiaoling, CN
• David Vigar · Singapore, SG

Key dates

• Filing date: Sep 17, 2003
• Grant date: Sep 7, 2004
• Expiry date: Oct 30, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/018

Abstract

A method of forming a double-gated transistor comprising the following sequential steps. A substrate having an SOI structure formed thereover is provided. The SOI structure including a lower SOI oxide layer and an upper SOI silicon layer. The SOI silicon layer is patterned to form a patterned SOI silicon layer including a source region and a drain region connected by a channel portion. An encasing oxide layer is formed over the patterned SOI silicon layer to form an encased patterned SOI silicon layer. A patterned dummy layer is formed over the encased patterned SOI silicon layer. The patterned dummy layer having an opening, with exposed side walls, exposing: the channel portion of the encased patterned SOI silicon layer; and portions of the upper surface of the SOI oxide layer. Offset spacers are over the exposed side walls of the patterned dummy layer opening. The SOI oxide layer is etched while minimizing the undercut portions of the upper surface of the SOI oxide layer are undercut into the SOI oxide layer to form a minimal undercut. The minimizing undercutting process also removing the offset spacers and the encasing oxide layer over the channel portion of the patterned SOI si…