Method for gross input leakage functional test at wafer sort
US6788095B1 · kind B1 · utility
7Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2003 |
| Grant date | Sep 7, 2004 |
| Priority date | — |
| Expiry date | Jan 31, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318505
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and test configuration for performing a gross input leakage test at wafer sort is described. The method uses a pullup and pulldown on an I/O pad to inject current at the I/O pad, and, based on the resulting voltage, determines if the leakage current is excessive. The method allows an input leakage test to be performed at wafer sort without a precision measurement unit and without direct access to the I/O pad to be tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.