Charge-trapping memory arrays resistant to damage from contact hole information
US6794764B1 · kind B1 · utility
27Cited by
6References
20Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Mar 5, 2003 |
| Grant date | Sep 21, 2004 |
| Priority date | — |
| Expiry date | Jul 15, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
Abstract
The present invention relates to a memory array comprising a substrate and a plurality of bitlines having contacts and a plurality of wordlines intersecting the bitlines. A protective spacer is used to separate the bitline contacts from the wordlines adjacent to the bitline contacts to prevent damage caused during the formation of the bitline contacts. The present invention also relates to a method of forming the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.