Copper damascene with low-k capping layer and improved electromigration reliability

US6797652B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Minh Van Ngo · Fremont, US
• Jeremy I. Martin · Austin, US
• Hartmut Ruelke · Dresden, DE

Key dates

• Filing date: Mar 15, 2002
• Grant date: Sep 28, 2004
• Expiry date: Apr 6, 2022

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/931
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The electromigration resistance of Cu lines is significantly improved by depositing a low-k capping layer thereon, e.g., a silicon carbide capping layer having a dielectric constant of about 4.5 to about 5.5. Embodiments include sequentially treating the exposed planarized surface of inlaid Cu with a plasma containing NH3 diluted with N2, discontinuing the plasma and flow of NH3 and N2, pumping out the chamber; introducing trimethylsilane, NH3 and He, initiating PECVD to deposit the silicon carbide capping layer, as at a thickness of about 200 å to about 800 å. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.