Patent · US Expired

Field effect transistor with reduced gate delay and method of fabricating the same

US6798028B2 · kind B2 · utility

6Cited by

19References

23Claims

0Family size

Assignee

Advanced Micro Devices, Inc. · US

Inventors

Manfred Horstmann · Dresden, DE
Rolf Stephan · Dresden, DE
Karsten Wieczorek · Dresden, DE
Stephan Kruegel · Sankt Goar, DE

Key dates

Filing date	May 2, 2001
Grant date	Sep 28, 2004
Priority date	—
Expiry date	Aug 3, 2021

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/663
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A transistor formed on a substrate comprises a gate electrode having a lateral extension at the foot of the gate electrode that is less than the average lateral extension of the gate electrode. The increased cross-section of the gate electrode compared to the rectangular cross-sectional shape of a prior art device provides for a significantly reduced gate resistance while the effective gate length, i.e., the lateral extension of the gate electrode at its foot, may be scaled down to a size of 100 nm and beyond. Moreover, a method for forming the field effect transistor described above is disclosed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.