Method of controlling wafer charging effects due to manufacturing processes
US6800562B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2003 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Mar 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention is generally directed to various methods of controlling wafer charging effects due to manufacturing processes, and a system for performing same. In one illustrative embodiment, the method comprises identifying a process metric associated with a process operation that is capable of generating a charge that is stored in at least one of a process layer and a feature formed above a substrate. In other embodiments, the method involves establishing a metric for a plasma-based process operation. The methods include establishing an allowable range for the process metric based upon data obtained from at least one electrical test performed on at least one semiconductor device subjected to the process operation, performing the process operation and indicating an alarm condition if the process metric associated with the process operation is not within the allowable range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.