Memory architecture with series grouped by cells
US6800890B1 · kind B1 · utility
6Cited by
6References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2002 |
| Grant date | Oct 5, 2004 |
| Priority date | — |
| Expiry date | Dec 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An IC with a memory array having a series architecture is disclosed. A memory cell of a series group comprises a transistor coupled to a capacitor in parallel. The capacitor includes first and second subcapacitors, one stacked one on top of the other. Providing a capacitor with two or more subcapacitors in a stack advantageously increases the capacitance of a capacitor without increasing surface area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.