Integrated circuit configuration and method of fabricating a dram structure with buried bit lines or trench capacitors

US6800898B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Annalisa Cappelani · Dresden, DE
• Bernhard Sell · Dresden, DE
• Josef Willer · Riemerling, DE

Key dates

• Filing date: Sep 12, 2001
• Grant date: Oct 5, 2004
• Expiry date: May 18, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/053

Abstract

The bottom and the sides of a lower part of recess formed in the substrate has an insulating structure. A first part of the conductive structure of a first electric conductivity type is located in the lower part of the recess. A second part of the conductive structure of a second electric conductivity type, lower than the first type, is located in an upper part and borders the region of the substrate at the sides of the recess. The conductive structure has a diffusion barrier between its first and second parts. The conductive structure is configured as a bit line of a DRAM cell configuration with a vertical transistor, whereby S/Du represents the lower source/drain area and S/Do represents the upper source/drain area connected to a memory capacitor. Or, the conductive structure is configured as a memory capacitor and the upper source drain/area is connected to a bit line.