Liner for semiconductor memories and manufacturing method therefor

US6803265B1 · kind B1 · utility

Assignee

• FASL LLC · US

Inventors

• Minh Van Ngo · Fremont, US
• Arvind Halliyal · Cupertino, US
• Tazrien Kamal · Atlanta, US
• Hidehiko Shiraiwa · San Jose, US
• Rinji Sugino · San Jose, US
• Dawn Hopper · San Jose, US
• Pei-Yuan Gao · San Jose, US

Key dates

• Filing date: Mar 27, 2002
• Grant date: Oct 12, 2004
• Expiry date: Apr 5, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3011
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A manufacturing method for an integrated circuit memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, ultra-violet block data retention liner covers the wordline and the charge-trapping dielectric layer. The reduced hydrogen levels reduce the charge loss compared to prior art. The surface of the liner is processed to block UV light before completing the integrated circuit.