Patent · US Expired

Trench buried bit line memory devices and methods thereof

US6806137B2 · kind B2 · utility

51Cited by
21References
39Claims
0Family size

Assignee

Inventors

Key dates

Filing dateNov 11, 2003
Grant dateOct 19, 2004
Priority date
Expiry dateNov 11, 2023

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10B12/485

Abstract

A memory device such as a 6F2 memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.