Low temperature method of forming a gate stack with a high k layer deposited over an interfacial oxide layer
US6806145B2 · kind B2 · utility
25Cited by
15References
38Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2002 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Aug 22, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28167
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to methods for forming dielectric layers on a substrate, such as in an integrated circuit. In one aspect of the invention, a thin interfacial layer is formed. The interfacial layer is preferably an oxide layer and a high-k material is preferably deposited on the interfacial layer by a process that does not cause substantial further growth of the interfacial layer. For example, water vapor may be used as an oxidant source during high-k deposition at less than or equal to about 300° C.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.