Method and system for scaling nonvolatile memory cells

US6806155B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Kelwin Ko · San Jose, US
• Chi Chang · Redwood City, US

Key dates

• Filing date: May 15, 2002
• Grant date: Oct 19, 2004
• Expiry date: Jul 5, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A method and system for providing a semiconductor device are described. The method and system include providing a plurality of gate stacks and a first source drain halo implant. The first source and drain halo implant uses the plurality of gate stacks as a mask. The method and system also include providing a lightly doped source and drain implant and a N+ source and drain implant. The source connection implant is for connecting a portion of the plurality of sources. The second source and drain implant uses the plurality of gate stacks as a mask. Moreover, CoSi formed on the source region provides a lower resistence for lines connecting the sources, allowing a lower dose to be used for the N+ source and drain implant.