System and method for time slicing deterministic patterns for reseeding in logic built-in self-test
US6807646B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2002 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Apr 29, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318328
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method for time slicing deterministic patterns for reseeding in logic built-in self-test (BIST). The known properties of a linear feedback shift register (LFSR) and an associated set of channels are used in conjunction with a desired deterministic test pattern to create one or more seeds which can be used by the LFSR to generate the test pattern. The test pattern is divided into a number of segments, with each segment having a specific number of “care” bits. The number of shifts required to fill a segment using a particular seed is stored along with the seed as a seed lifetime. During testing, each deterministic test pattern is generated by loading a seed into the LFSR and cycling the LFSR in accordance with the lifetime of the seed. The seed lifetimes may have different values, and multiple seeds may be used in the generation of a single test pattern, or a single seed may be used to generate care bits of multiple test patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.