Process for making a gate for a short channel CMOS transistor structure
US6818488B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 8, 2003 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Sep 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a process for making a gate for a CMOS transistor structure, made from a stack realized on a face in a semi-conducting material of a substrate, said stack comprising a gate isolation layer, a gate material layer and a gate mask in sequence, the process comprising the following steps:a) anisotropic etching of the top part of the gate material layer not masked by the gate mask, this etching step leaving the bottom part of the gate material layer and leading to the formation of a deposit composed of etching products on the etching sides resulting from the anisotropic etching,b) treatment of the deposit composed of etching products, to make a protection layer reinforced against subsequent etching of the gate material,c) etching of the bottom part of the gate material layer as far as the gate isolation layer, this etching comprising isotropic etching of the gate material layer to make the gate shorter at the bottom than at the top.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.