Laurent Vallier
9Patents
3h-index
23Co-inventors
57Inventor score
Filing activity: Nov 22, 1989 → Dec 17, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5102687A | Process for surface treatment by plasma of a substrate supported by an electrode | Chemistry; Metallurgy | 15 | Expired |
| US9570317B2 | Microelectronic method for etching a layer | Electricity | 11 | Active |
| US6818488B2 | Process for making a gate for a short channel CMOS transistor structure | Electricity | 4 | Expired |
| US10062602B2 | Method of etching a porous dielectric material | Electricity | 3 | Active |
| US9583339B2 | Method for forming spacers for a transistor gate | Electricity | 3 | Active |
| US8956886B2 | Embedded test structure for trimming process control | Electricity | 2 | Active |
| US6551698B1 | Method for treating a silicon substrate, by nitriding, to form a thin insulating layer | Emerging Cross-Sectional Technologies | 1 | Expired |
| US9048011B2 | Method of obtaining patters in an antireflective layer | Electricity | 0 | Active |
| US11380543B2 | Method for fabricating a monocrystalline structure | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.