Memory device having resistive element coupled to reference cell for improved reliability
US6819615B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2002 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Nov 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reference cell transistor with a series resistance to improve reliability in reading cells in an associated memory array. The reference cell transistor is coupled in series with a resistive element such that a reference current flows therethrough to reduce a voltage between a gate and a source of the reference cell transistor. This bends the Ids versus Vgate curve of the reference cell downward and compensates for irregularities in the resistance seen in series with the memory cell transistors. In this fashion, the margin when reading memory cells is improved and the reference current is more reliable. The resistive element may be external to a region having the reference cell transistor. Alternatively, the resistive element may be internal to a region with the memory array and reference cell. For example, it may be formed by extending the source region of the reference cell transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.