Interconnect test structure with slotted feeder lines to prevent stress-induced voids
US6822437B1 · kind B1 · utility
20Cited by
4References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2003 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | Feb 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/34
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnect test structure for characterizing electromigration includes a test line and a feeder coupled to the test line by a via structure. A width of the feeder line is greater than a width of the test line. Slots are formed in the feeder line for preventing formation of a stress-induced void at an interface between the feeder line and the via structure. Thus, an increase in resistance of the test structure is attributable to electromigration failure of the test line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.