Method for providing high availability within a data processing system via a reconfigurable hashed storage subsystem
US6823471B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1999 |
| Grant date | Nov 23, 2004 |
| Priority date | — |
| Expiry date | Jul 1, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the execution resources and the data storage, that supplies instructions within the data storage to the execution resources. At least one of the execution resources, the data storage, and the instruction sequencing unit is implemented with a plurality of hardware partitions of like function for processing a respective one of a plurality of data streams. If an error is detected in a particular hardware partition, the data stream assigned to that hardware partition is reassigned to another of the plurality of hardware partitions, thus preventing an error in one of the hardware partitions from resulting in a catastrophic failure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.