2T2C signal margin test mode using a defined charge and discharge of BL and /BL
US6826099B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2002 |
| Grant date | Nov 30, 2004 |
| Priority date | — |
| Expiry date | Nov 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory test mode configuration includes a first capacitor for storing digital data. The first capacitor connects a cell plate line to a first bit line through a first select transistor which is activated through a connection to a word line. A second capacitor for storing digital data connects the cell plate line to a second bit line through a second select transistor which is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines. A constant current mover, for example a constant current sink or source, is connected to the first bit line through a third transistor for changing the amount of charge on the first bit line when the third transistor is turned on to reduce the differential read signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.