Structure and method for reducing thermo-mechanical stress in stacked vias

US6831363B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Timothy J. Dalton · Ridgefield, US
• Sanjit Das · Poughkeepsie, US
• Brett H. Engel · Fishkill, US
• Brian Herbst · Poughquag, US
• Habib Hichri · Snyder, US
• Bernd Kastenmeier · Austin, US
• Kelly Malone · Delmar, US
• Jeffrey R. Marino · Fishkill, US
• Arthur Winston Martin · Horseheads, US
• Vincent J. McGahay · Poughkeepsie, US
• Ian D. Melville · Highland, US
• Chandrasekhar Narayan · Hopewell Junction, US
• Kevin S. Petrarca · Newburgh, US
• Richard P. Volant · New Fairfield, US

Key dates

• Filing date: Dec 12, 2002
• Grant date: Dec 14, 2004
• Expiry date: Dec 12, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/12044
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.