ESD protection structure

US6835985B2 · kind B2 · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Jun Cai · Allen, US
• Guang Ping Hua · Singapore, SG
• Jun Song · Suwon-si, KR
• Keng Foo Lo · Singapore, SG

Key dates

• Filing date: Dec 9, 2000
• Grant date: Dec 28, 2004
• Expiry date: Jun 12, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002

Abstract

A transistor structure is provided for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.