Protection of low-k ILD during damascene processing with thin liner

US6836017B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Minh Van Ngo · Fremont, US
• Christy Mei-Chu Woo · Cupertino, US
• Steven C. Avanzino · Cupertino, US
• John Sanchez · Palo Alto, US
• Suzette K. Pangrle · Cupertino, US

Key dates

• Filing date: Jan 20, 2004
• Grant date: Dec 28, 2004
• Expiry date: Jan 20, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76807
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.