Method and system for delay control in synchronization circuits
US6836166B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2003 |
| Grant date | Dec 28, 2004 |
| Priority date | — |
| Expiry date | Jan 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/087
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A synchronization circuit includes a first and second phase-shifting path circuit, with each generates a phase-shifted signal responsive to an input signal and the phase-shifted signal having respective fine and coarse phase shifts relative to the input signal. Each phase-shifting path circuit adjusts the coarse and fine phase shifts responsive to control signals. A selection circuit outputs one of the phase-shifted signals responsive to a selection signal. A control circuit monitors a phase shift between the input signal and the output phase-shifted signal and develops the selection and control signals to select one of the phase-shifting path circuits and to adjust the fine phase shift of the selected path circuit and the fine and coarse phase shifts of the other path circuit. When the fine delay of the selected phase-shifting path circuit has a threshold value, the control circuit develops the selection signal to select the other phase-shifting circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.