Method for forming a passivation layer for air gap formation

US6838354B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Cindy Goldberg · Cold Spring, US
• Stanley M. Filipiak · Pflugerville, US
• John C. Flake · Meylan, FR
• Yeong-Jyh T. Lii · Austin, US
• Bradley P. Smith · Youngstown, US
• Yuri Solomentsev · Austin, US
• Terry G. Sparks · Austin, US
• Kirk Strozewski · Round Rock, US
• Kathleen C. Yu · Austin, US

Key dates

• Filing date: Dec 20, 2002
• Grant date: Jan 4, 2005
• Expiry date: Dec 23, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76874
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.