Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing
US6841441B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2003 |
| Grant date | Jan 11, 2005 |
| Priority date | — |
| Expiry date | Jan 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/268
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.