Memory cell, memory cell configuration and fabrication method

US6844584B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Herbert Palm · Hohenkirchen, DE
• Josef Willer · Riemerling, DE
• Achim Gratz · Dresden, DE
• Jakob Kriz · Ochtrup, DE
• Mayk Roehrich · Dresden, DE

Key dates

• Filing date: Aug 9, 2001
• Grant date: Jan 18, 2005
• Expiry date: Aug 9, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/69

Abstract

Each memory cell is a memory transistor which is provided on a top side of a semiconductor body and has a gate electrode which is arranged in a trench located between a source region and a drain region that are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by a dielectric material. At least between the source region and the gate electrode and between the drain region and the gate electrode, there is an oxide-nitride-oxide layer sequence. The layer sequence is provided for the purpose of trapping charge carriers at the source and the drain.