Low profile semiconductor device having improved heat dissipation

US6847102B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Mark A. Gerber · Lucas, US
• Bennett A. Joiner · Austin, US
• Jose Antonio Montes De Oca · New Braunfels, US
• Trent Thompson · Austin, US

Key dates

• Filing date: Nov 8, 2002
• Grant date: Jan 25, 2005
• Expiry date: Nov 8, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/18165
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A package substrate (12, 52) has a first surface, a second surface opposite a first surface, and a cavity (22, 70) formed in the first surface that extends into the package substrate. The cavity has a cavity wall substantially perpendicular to the first and second surfaces. An integrated circuit die (20, 60) is placed in the cavity, and a conductive material (24, 72) is placed in the cavity to thermally couple an outer wall of the integrated circuit to the cavity wall. The conductive material improves the heat dissipation path between the integrated circuit die and the package substrate. The cavity may extend through the package substrate to the second surface such that the second surface of the package substrate is substantially coplanar to a surface of the integrated circuit die. An encapsulation layer (28, 78) may be formed over the conductive material, integrated circuit die, and at least a portion of the first surface of the package substrate.