Methods of forming drain/source extension structures of a field effect transistor using a doped high-k dielectric layer

US6849516B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Thomas Feudel · Radebeul, DE
• Manfred Horstmann · Dresden, DE
• Karsten Wieczorek · Dresden, DE
• Stephan Kruegel · Sankt Goar, DE

Key dates

• Filing date: May 21, 2003
• Grant date: Feb 1, 2005
• Expiry date: May 21, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0212
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

According to one illustrative embodiment of the present invention, a method of forming a field effect transistor includes the formation of a doped high-k dielectric layer above a substrate including a gate electrode formed over an active region and separated therefrom by a gate insulation layer. A heat treatment is carried out with the substrate to diffuse dopants from the high-k dielectric layer into the active region to form extension regions. The high-k dielectric layer is patterned to form sidewall spacers at sidewalls of the gate electrode and an implantation process is carried out with the sidewall spacers as implantation mask to form source and drain regions.