Noise reduction technique for transistors and small devices utilizing an episodic agitation
US6850441B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2002 |
| Grant date | Feb 1, 2005 |
| Priority date | — |
| Expiry date | Feb 3, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0458
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect is applicable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.